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ir3720 data sheet page 1 of 20 www.irf.com 09/09/08 power monitor ic with digital i 2 c interface features ? accurate truepower ? monitor ? minimizes dynamic errors ? reports voltage, current, or power ? digital interface ? smbus and i 2 c compatible ? programmable averaging interval ? flexible current sensing ? resistive or inductor dcr ? applications ? synchronous rectified buck converters ? multiphase converters ? 10pin 3x3 dfn lead free package ? rohs compliant description the ir3720 measures the output voltage and inductor current of low-voltage dc-to-dc converters and reports the average power over a user specified time interval as a digital word on the i 2 c. the output current is measured across a current sensing resistor or indirectly across the inductors dcr winding resistance. additionally, the current m easurement method is also applicable to multiphase converters. the real time voltage and current signals are multiplied, digitized, and averaged over a user selectable averaging interval providing patent pending truepower? measurement of highly dynamic loads. typical application circuit r cs1 vcs l dcr load vdd i 2 c bus phase power return to system controller ir3720 single phase converter gnd vo 3.3v gnd v ref r t c cs1 r cs2 c cs2 output capacitors 2 ordering information device package order quantity IR3720MTRPBF 10 lead dfn (3x3 mm body) 3000 piece reel * ir3720mpbf 10 lead dfn (3x3 mm body) 121 piece tube * samples only downloaded from: http:///
ir3720 data sheet page 2 of 20 www.irf.com 09/09/08 absolute maximum ratings all voltages referenced to gnd vdd: ................................................................3.9v alert#:...........................................................3.9v alert#.............................................. ir3720 data sheet page 3 of 20 www.irf.com 09/09/08 note: 1. guaranteed by design, not tested in production 2. average of eight data samples parameter test condition min typ max unit digitizer internal sampling frequency driven from internal clock 435 512 589 khz external sampling frequency driven from external clock 922 1024 1126 khz transition time driven from external clock note 1 50 ns power information minimum averaging interval config reg [d 3..d0] = b0000, note 1 0.9 1 1.1 ms maximum averaging interval config reg [d3..d0] = b1000, note 1 230 256 282 ms output register measuring power vo=1v; v dcr =20 mv r cs2 =600 ? , r t =25.5 k ? , note 1,2 1380 1440 1500 hex output register measuring power vo=0.5v; v dcr =20 mv r cs2 =600 ? , r t =25.5 k ? , note 1,2 0980 0a00 0a80 hex output register measuring power vo=1v; v dcr =0 mv r cs2 =600 ? , r t =25.5 k ? , note 1,2 ff40 0000 00c0 hex output register measuring power vo=1v; v dcr =-8 mv r cs2 =600 ? , r t =25.5 k ? , note 1,2 f740 f800 f8c0 hex full scale output register measuring power vo = 1.8; v dcr =35 mv r cs2 =600 ? , r t =25.5 k ? , note 1,2 3dc0 3f80 4000 hex digital input and output alert# pull down resistance sink 3 ma 250 sda & scl high level note 1 2.1 v sda & scl low level note 1 0.8 v scl input current note 1 -5 +5 ua sda pull down voltage sink 4 ma note 1 0.4 v timing maximum frequency note 1 10 400 khz bus free time between stop and start t buf note 1 1.3 us hold time after (repeated) start condition t hd:sta note 1 0.6 us repeated start condition setup time t su:sta note 1 0.6 us stop condition setup time t su:sto note 1 0.6 us data hold time t hd:dat note 1 300 ns data setup time t su:dat note 1 100 ns clock low period t low note 1 1.3 us clock high period t high note 1 0.6 us clock or data fall time t f note 1 20 300 ns clock or data rise time t r note 1 20 300 ns downloaded from: http:///
ir3720 data sheet page 4 of 20 www.irf.com 09/09/08 system accuracy test circuit vdd vref gnd scl sda extclk addr vcs vo alert# c cs2 r cs2 vdd bypass cap vdd r t v dcr vo downloaded from: http:///
ir3720 data sheet page 5 of 20 www.irf.com 09/09/08 block diagram ic pin description name number i/o level description vcs 1 analog current sensing input vo 2 analog voltage sensing input vref 3 analog thermistor sensing input gnd 4 ic bias supply and signal ground vdd 5 3.3v 3.3v bias supply extclk 6 3.3v digital input for optional external clock addr 7 3.3v digital i 2 c address selection input; see table 1 for address scl 8 3.3v digital i 2 c clock; input only sda 9 3.3v digital i 2 c data; input / open drain output alert# 10 3.3v digital programmable output function; open drain output clamped to vdd base pad connect to pin 4 downloaded from: http:///
ir3720 data sheet page 6 of 20 www.irf.com 09/09/08 ic pin functions vdd pin this pin provides operational bias current to circuits internal to the ir3720. bypass it with a high quality ceramic capacitor to the gnd pin. gnd pin this pin returns operational bias current to its source. it is also the reference to which the voltage vo is measured, and it sinks the reference current established by the external resistor r t . vo pin connect this pin to the location in the circuit where voltage for the power calculation is desired to be monitored. since it also measures dcr voltage drop it is critical that it be kelvin connected to the buck inductor output. power accuracy may be degraded if the voltage at this pin is below vo min . vcs pin the average current into this pin is used to calculate power. a switched current source internal to the ir3720 will maintain the aver age voltage of this pin equal to the voltage of the vo pin. vref function a voltage reference internal to the ir3720 drives the v ref pin while the pin current is monitored and used to set the amplitude of the current monitor switched current source i ref . this pin should be connected to gnd through a precision resistor network r t . this network may include prov ision for canceling the positive temperature coefficient of the buck inductors dc resistance (dcr). alert# function the alert# pin is a multi-use pin. during normal use it can be configured via the i 2 c as an open drain alert# pin that will be driven logic low when new data is available in the output register. after the output register has been read via the i 2 c the alert# will be released to its high re sistance state. this pin can also be programmed to pull low when the output exceeds the programmable level. addr pin the addr pin is an input that establishes the i 2 c address. valid addresses are selected by grounding, floating, or wiring to vdd the addr pin. table 1, user selectable addresse s, provides a mapping of possible selections. table 1 user selectable addresses addr pin configuration i 2 c address low b1110 000 open b1110 010 high b1110 110 extclk this pin is a schmitt trigger input for an optional externally provided square wa ve clock. the duty ratio of this externally provided clock, if used, shall be between 40% and 60%. if no external clock is used, connect this pin to gnd and the internal clock will be used. scl scl is the i 2 c clock and is capable of functioning with a rate as low as 10 khz. it will continue to function as the rate is increased to 400 khz. this device is considered a slave, and therefore uses the scl as an input only. sda sda is monitored as data input during master to slave transactions, and is driven as data output during slave to master transactions as indicated in the packet protocol section to follow. downloaded from: http:///
page 7 of 20 www.irf.com 09/09/08 typical performance characteristics (system accuracy test circuit, vdd=3.3 v, r cs2 = 600 ? , c cs2 = 1 f, r t = 25.5 k ? ) typical transfer characteristic - power configuration average of 8 samples -300 0 300 -0.035 0.000 0.035 v dcr (v) codes (decimal) vo = 0.5v vo = 1.0v vo = 1.8v ideal code typical error - power configuration average of 8 samples 0 1 2 3 4 5 6 7 8 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 v dcr (v) error (%) vo = 1.0v vo = 1.8v typical error - current configuration average of 8 samples 0 1 2 3 4 5 6 7 8 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 v dcr (v) error (%) vo = 0.5v vo = 1.0v vo = 1.8v downloaded from: http:///
page 8 of 20 www.irf.com 09/09/08 functional description please refer to the functional description diagram below. power flow from the buck converter is the product of output voltage times the current i l flowing through the inductor. average power is measured with the aid of international rectifiers proprietary truepower? circuit. voltage, current, or the product of voltage vo and current is digitized over the interval of interest and ported to the output register. the vcs pin is maintained at an average voltage equal to vo. the full-scale voltage that can be measured is v fs . the full-scale positive curr ent that can be measured is ( ) dcr r r r v i 2cs 1cs t ig fs + ? = . (1) full-scale current capability is designed by specifying the external circuit values of equation 1. the full scale power p fs that can be measured is the product of full-scale voltage and full scale current. vdd v ref gnd scl sda extclk addr vcs vo alert# r cs1 l dcr phase i l c cs2 c cs1 r cs2 vo vin ir3720 vdd bypass cap alert# pull-up resistor vdd external clock r t figure 1 functional description diagram downloaded from: http:///
page 9 of 20 www.irf.com 09/09/08 resistor sensing application the voltage on the shunt resistor of the circuit below is directly proportional to the current from the source. shunts developing 5 mv to 75 mv at i fs have been used. accuracy is enhanced at the higher voltage. select r t to be a 25.5 k ? 1% or better initial tolerance resistor. this value will sink 1.5v /r t of current from the vref pin of the ir3720. r cs2 should be chosen such that this current through it develops the same voltage that is developed by the shunt at full scale current. c cs2 is the integrator capacitor and should be between 0.1 f and 10 f. vdd v ref gnd scl sda extclk addr vcs vo alert# l dcr phase i l c cs2 r cs2 vo vin ir3720 vdd bypass cap vdd shunt r t figure 2 resistor sensing circuit downloaded from: http:///
page 10 of 20 www.irf.com 09/09/08 inductor dcr current sensing application referring to the functional description diagram, it can be seen that the shunt function can be accomplished by the dc resi stance of the inductor that is already present. omitting the resistive shunt reduces bom cost and increases efficiency. in exchange for these two si gnificant advantages two easily compensated design complications are introduced, a time constant and a temperature coefficient. the inductor voltage sensed between the rcs1 resistors is not simply proportional to the inductor current, but rather is expressed in the laplace equation below. ?? ? ?? ? + ?= dcr l s 1 dcr l l v this inductor time constant is canceled when cs1 cs2 cs1 cs2 cs1 c r r r r dcr l ? + ? = . let eq cs2 cs1 cs2 cs1 r r r r r = + ? . a second equation is used to set the full scale inductor current. () dcr r r r v i cs2 cs1 t ig fs + ? = . let sum cs2 cs1 r r r = + and solve for rsum. select a standard value c cs1 that is larger than sum r dcr l4 ? ? . solve for r eq . we now know req and rsum, but we do not know the individual resistor values r cs1 or r cs2 . the next step is to solve for them simultaneously. by substituting r sum into the r eq equation the following can be written: sum cs2 cs1 eq r r r r ? = , which can then be rearranged to 0 r r r r r sum eq sum cs1 2 cs1 = ? + ? ? . note that this equation is of the form 0 c bx ax 2 = + + where a=0, b=-rsum, and c=reqrsum. the roots of this quadratic equation will be r cs1 and r cs2 . use the higher value resistor as r cs1 in order to minimize ripple current in c cs1 . 2 r r 4 1 1 r r sum eq sum cs1 ? ? + ? = and 2 r r 4 1 1 r r sum eq sum cs1 ? ? ? ? = downloaded from: http:///
page 11 of 20 www.irf.com 09/09/08 thermal compensation fo r inductor dcr current sensing the positive temperature coefficient of the dcr can be compensated if r t varies inversely proportional to the dcr. dcr of a copper coil, as a function of temperature, is approximated by ) ) ( 1() ( )( cu r r tcr t t t dcr t dcr ? ? + ? = . (2) t r is some reference temperature, usually 25 c, and tcr cu is the resistive temperature coefficient of copper, usually assumed to be 0.0039 near room temperature. note that equation 2 is linearly increasing with temperature and has an offset of dcr(t r ) at the reference temperature. if r t incorporates a negative temperature coefficient thermistor then temperatur e effects of dcr can be minimized. consider a circ uit of two resistors and a thermistor as shown below. rs rth rp figure 3 r t network if rth is an ntc thermistor then the value of the network will decrease as temperature increases. unfortunately, most thermistors exhibit far more variation with temperature than copper wire. one equation used to model thermistors is ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? = 0 11 0 )( )( tt th th e t r t r (3) where r th (t) is the thermistor resistance at some temperature t, r th (t 0 ) is the thermistor resistance at the reference temperature t 0 , and is the material constant provided by the thermistor manufacturer. degrees kelvin are used in equation 3. if r s is large and r p is small, the curvature of the effective network resistance can be reduced from the curvature of the thermistor alone. although the exponential equation 3 can never compensate linear equation 2 at all temperatures, a spreadsheet can be constructed to minimize error over the temperature interval of interest. the resistance r t of the network shown as a function of temperature is )( + + =)( t r 1 r 1 1 r t r th p s t (4) using r th (t) from equation 3. equation 1 of the last section may be rewritten as a new function of temperature using equations 2 and 4 as follows: () )( + ? )( =)( t dcr r r t r v t i 2cs 1cs t ig fs . (5) with rs and rp as additional free variables, use a spreadsheet to solve equation 5 for the desired full scale current while minimizing the i fs (t) variation over temperature. downloaded from: http:///
page 12 of 20 www.irf.com 09/09/08 typical 2-phase dcr-sensing application the ir3720 is capable of monitoring power in a multiphase converter. a two-phase circuit is shown below. the voltage output of any phase is equal to that of any and every other phase, and monitored at vo as before. output current is the sum of the two inductor currents (i l1 + i l2 ). superposition is used to derive the transfer function for multiphase sensing. the voltage on r cs2 due to i l1 is ) || ( ) || ( 3 2 1 3 2 1 1 cs cs cs cs cs l r r r r r dcr i + ? ? likewise, the voltage on r cs2 due to i l2 is ) || ( ) || ( 1 2 3 1 2 2 2 cs cs cs cs cs l r r r r r dcr i + ? ? the current through r cs2 due to both inductor currents is i cs . from the two equations above 3 2 3 1 2 1 1 2 2 3 1 1 cs cs cs cs cs cs cs l cs l cs r r r r r r r dcr i r dcr i i + + + = if dcr 1 =dcr 2 , and r cs1 =r cs3 , then i cs can be simplified to 2 1 1 2 1 2 ) ( cs cs l l cs r r dcr i i i + ? + = full scale i cs current corresponds to t ig csfs r v i = which yields 256 digital current counts (0100 0000 0000 0000). full scale total inductor current is dcr r 2 r r v i i 2cs 1cs t ig fs 2l 1l ) ? + ( ? = ) + ( r cs1 vcs l dcr 1 l dcr 2 r cs3 load vdd i 2 c bus phase 1 phase 2 power return to system controller ir3720 multiphase converter gnd vo 3.3v rtn v ref ics i l1 i l2 r t t r cs2 c cs1 c cs2 2 figure 4two phase dcr sensing circuit downloaded from: http:///
page 13 of 20 www.irf.com 09/09/08 error management component value errors external to the ir3720 contribute to power and cu rrent measurement error. the power reported by the ir3720 is a function not only of actual power or current, but also of products and quotients of r t , r cs1 , r cs2 , dcr (or r shunt ), as well as parameters internal to the ir3720. the tolerance of these components increases the total power or current error. sm all signal resistors are typically available in 1% tolerance, but 0.1% parts are available. shunts are also available at 1% or 0.1% tolerance. the dcr tolerance of inductors can be 5%, but 3% are available. fort unately, it is not typical that worst-case errors woul d systematically stack in one direction. it is statistically likely that a high going value would be paired with a low going value to somewhat cancel the error. because of this, tolerances can be added in quadrature (rss). as an example, a 3% dcr used with a 1% r t , a 1% r cs , and 3.3% ir3720 contributes % . ) .(+).(+).(+) .( 74 033 0 01 0 01 0 03 0 2 2 2 2 error to a typical system. quantization error occurs in digital systems because the full scale is partitioned into a finite number of intervals and the number of the interval containing the measured value is reported. it is not likely that the measured value would correspond exactly to the center of the interval. the error could be as large as half the width of the interval. with a binary word size of eight, full scale is partitioned into 255 intervals. consider a measurement made near full scale. any signal in this interval is less than .2% (one-half of 100% / 256) away from the intervals center, and would therefore never have more error than that due to quantization. on the other hand, consider a measurement at one-tenth full scale. one-half of an interval size at this level corresponds to 2% of the reported value! relative quantization error increases as the measured value becomes small compared to the full-scale value. quantization error can be reduced by averaging a sequence of returned values. downloaded from: http:///
page 14 of 20 www.irf.com 09/09/08 configuration register a configuration register is maintained via the i 2 c mfr_specific_00 command, code # d0h. the low order nibble (d3, d2, d1, d0) contains a binary number n from zero to eight. the averaging interval is 2 n milliseconds. n defaults to zero on start up. the next bit (d4) is to be used as a function enable bit. b1 commands an energy saving shut down mode, and power on default b0 commands fully functioning mode. d5 high enables the extclk pin to receive the external clock signal, and default d5 low enables the internal clock. the next two bits (d7, d6) program the output parameter. b00 causes power to be measured and is the power on default state. b01 causes voltage to be measured. b10 causes current to be measured. b11 is not defined and should not be used. the next bit (d8) is used to configure the alert# pin. b0 is the power on default, and commands alert# being pulled low when new data is available. b1 programs the alert# to pull low when the programmable threshold level is exceeded, whether it is power, voltage, or current. register bits (d15...d9) are the alert# threshold register. if the output register is larger than this register, and if (d8) is b1, then the alert# pin will pull low. the two least significant bits of the output register are not represented in the alert# threshold register. d15d9 defaults to zero on start up. the results of a configuration register change will be reflected in the output register after previously requested operations have completed. bit # configuration register d0 averaging interval (lsb) d1 averaging interval d2 averaging interval d3 averaging interval (msb) d4 enable d5 external clock d6 output config (lsb) d7 output config (msb) d8 alert# configuration d9 alert# threshold (lsb + 2) d10 alert# threshold d11 alert# threshold d12 alert# threshold d13 alert# threshold d14 alert# threshold d15 alert# threshold (msb) downloaded from: http:///
page 15 of 20 www.irf.com 09/09/08 output register the output register is loaded with a twos compliment factor of voltage, current, or power, depending on the last request loaded into the configuration register. i 2 c direct data format is used. the value of the output register is to be multiplied by a scale factor that is derived from equations 1 and 2 above. maximum power is the product of maximum voltage and maximum current. the range of valid values is indicated in table 2 below. table 2 output register range of returned values parameter returned value (twos compliment binary) returned value (decimal) fs voltage 0100 0000 0000 0000 256 zero voltage 0000 0000 0000 0000 0 +fs current 0100 0000 0000 0000 256 -fs current 1100 0000 0000 0000 -256 +fs power 0100 0000 0000 0000 256 -fs power 1100 0000 0000 0000 -256 a binary point is implicitly located to the left of the first six least significant figures, as in the example below. syyy yyyy yy.00 0000 the s above is the twos compliment sign bit, and the ys are the twos compliment. six zeros pad out the two byte response. these padding zeros could be considered a factor of the slope, which is allowed by the direct data format. the output register multiplied by its scale factor k x yields the requested quantity in engineering units of volts, amps, or watts. the equations below convert digital counts to engineering units: 256 v counts voltage fs ? = when configuration register bits (d7, d6) are set to (01). dcr r 256 r r v counts current t cs2 cs1 ig ? ? ) + (? ? = when configuration register bits (d7, d6) are set to (10). dcr r 256 r r v v counts power t cs2 cs1 ig fs ? ? ) + (? ? ? = when configuration register bits (d7, d6) are set to (00). there is but one output register, and it holds the measurement type (voltage, current, or power) last requested by the configuration register. it is incumbent upon the user to establish correct configuration before requesting a read. read_vout, read_iout, and read_pout are equivalent in that each returns the contents of the same output register. bit# output register d15:d0 output variable, d0 is lsb reserved command codes command codes d2h through d5h, d7h, and d8h are reserved for manufacturing use only and could lead to undesirable device behavior. downloaded from: http:///
page 16 of 20 www.irf.com 09/09/08 packet protocol s = start condition w = bus write (lo) r = bus read (hi) a = acknowledge, = 0 for ack, =1 for nack p = stop condition = master to slave = slave to master bus write configuration register s slave address w a command code a data byte low a data byte high ap s see table 1 0 a 1 1 0 1 0 0 0 0 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 ap bus read configuration register s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 1 0 1 0 0 0 0 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p bus read_vout (output register for config uration register data byte low = 01xxxxxx) s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 0 0 0 1 0 1 1 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p bus read_iout (output register for configuration register data byte low = 10xxxxxx) s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 0 0 0 1 1 0 0 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p bus read_pout (output register for config uration register data byte low = 00xxxxxx) s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 0 0 1 0 1 1 0 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p downloaded from: http:///
page 17 of 20 www.irf.com 09/09/08 pcb pad and component placement the figure below shows suggested pad and component placement. downloaded from: http:///
page 18 of 20 www.irf.com 09/09/08 solder resist the figure below shows the suggested solder resist placement. downloaded from: http:///
page 19 of 20 www.irf.com 09/09/08 stencil design the figure below shows a suggested stencil design. downloaded from: http:///
page 20 of 20 www.irf.com 09/09/08 package information 3x3 mm 10l dfn lead free data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa te l: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . downloaded from: http:///

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